Posted: 07 Nov 2010, 09:41
Just like the wait 1 cycle module for data streams is it possible to delay processing for an entire sub patch to compensate for the 1 bloc delay of bus send and recieve on multi core/thread systems?
BrainModular Users Forum
https://www.brainmodular.com/forums/
https://www.brainmodular.com/forums/viewtopic.php?f=6&t=2540